1. Field of Invention
The present invention generally relates to a semiconductor package, and more particularly, to a conductive bump formed for connection to an outside, a semiconductor chip and a stacked semiconductor package using the same.
2. Description of the Related Art
In the semiconductor industry, packaging technologies for semiconductor integrated circuits have continuously been developed to meet the demands toward miniaturization and mounting efficiency. Recently, as the miniaturization and high performance of electric and electronic appliances are demanded, various stacking techniques have been developed.
The term “stack” that is referred to in the semiconductor industry means to vertically pile at least two semiconductor chips or semiconductor packages. In the case of a memory device, by using a stacking technology, it is possible to realize a product having memory capacity at least two times greater than that obtainable through semiconductor integration processes, and mounting area utilization efficiency can be elevated.
In a conventional stacked semiconductor package, since signal transmission between stacked semiconductor chips is implemented by wires, a problem is caused in that an operation speed decreases. Also, since an additional area for wire bonding is needed in a substrate, the size of the stacked semiconductor package increases. Further, since a gap is needed to bond wires to the bonding pads of the respective semiconductor chips, the overall height of the stacked semiconductor package increases.
Thus, recently, in order to overcome the disadvantages of the conventional stacked semiconductor package, the structure of a stacked semiconductor package using through vias has been is suggested.
Referring to FIGS. 1 and 2, in a conventional stacked semiconductor package 10 using through vias, after defining via holes (not shown) in respective semiconductor chips 12, through vias 13 are formed by filling a metal layer in the via holes through a plating process, and the semiconductor chips 12 formed with the through vias 13 are stacked such that electrical connection between the semiconductor chips 12 is implemented through the through vias 13.
Therefore, in the stacked semiconductor package using the through vias 13, an additional area for wire bonding is not needed in a substrate 11, a gap is not needed to perform wire bonding between the semiconductor chips 12, and a signal transmission length to the respective semiconductor chips 12 is shortened. As a consequence, advantages are provided in that the overall size and height of the stacked semiconductor package may be decreased when compared to the conventional stacked semiconductor package, and the operation speed of the stacked semiconductor package may be improved.
Bumps 14 and 15 may be formed on the through vias 13 to serve as external connection terminals. In general, such bumps 14 and 15 are formed by forming a barrier metal on one surface or both surfaces of each of the semiconductor chips 12 to a predetermined thickness, aligning a mask and then performing etching.
After forming upper bumps 14 and lower bumps 15 of predetermined heights on the through vias 13 of the respective semiconductor chips 12 through such a process, semiconductor chips are stacked on the substrate 11. Then, solder balls 16 are attached to the lower surface of the substrate 11, and the plurality of stacked semiconductor chips 12 are encapsulated by an encapsulation member 17 such as epoxy resin, by which the stacked semiconductor package is manufactured. The numeral 15a indicates a connection member such as a solder.
When manufacturing the stacked semiconductor package using the through vias 13, underfill members 18 such as NCPs (non-conductive pastes) or NCFs (non-conductive films) are used to fill gaps between upper semiconductor chips and lower semiconductor chips. However, as shown in FIG. 2, in the conventional stacked semiconductor package, fillers 18a contained in the underfill members 18 which are added to increase a mechanical strength are likely to be trapped between the upper bumps 14 and the lower bumps 15, by which a connection fail may occur between the semiconductor chips 12 and the junction strength of the bumps 14 and 15 may be degraded.
That is to say, although it is advantageous in improving the connectivity of the stacked semiconductor chips 12 for the fillers 18a to be smoothly released out of the bumps 14 and 15 when is bonding an upper semiconductor chip and a lower semiconductor chip, since the bumps 14 and 15 are formed to have substantially flat upper surfaces, the lateral mobility of the fillers 18a may deteriorate, as a result of which a connection fail may occur between the semiconductor chips 12 and the junction strength of the bumps may be degraded.